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1.

電子ブック

EB
edited by Jesper Larsson Traff, Sascha Hunold, Francesco Versaci
出版情報: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2015
シリーズ名: Lecture Notes in Computer Science ; 9233
オンライン: http://dx.doi.org/10.1007/978-3-662-48096-0
目次情報: 続きを見る
Concurrent Systems: Hybrid Object Implementations and Abortable Objects
Runtime-Aware Architectures
MPI Thread-Level Checking for MPI+OpenMP Applications
Event-Action Mappings for Parallel Tools Infrastructures
Low-Overhead Detection of Memory Access Patterns and Their Time Evolution
Automatic On-line Detection of MPI Application Structure with Event Flow Graphs
Online Automated Reliability Classification of Queueing Models for Streaming Processing Using Support Vector Machines
A Duplicate-Free State-Space Model for Optimal Task Scheduling
On the Heterogeneity Bias of Cost Matrices when Assessing Scheduling Algorithms
Hardware Round-Robin Scheduler for Single-ISA Asymmetric Multi-Core
Moody Scheduling for Speculative Parallelization
Allocating Jobs with Periodic Demands
A Multi?Level Hypergraph Partitioning Algorithm Using Rough Set Clustering
Non-preemptive Throughput Maximization for Speed-Scaling with Power-Down
Scheduling Tasks from Selfish Multi-tasks Agents
Locality and Balance for Communication-Aware Thread Mapping in Multicore Systems
Concurrent Priority Queues Are not Good Priority Schedulers
Load Balancing Prioritized Tasks via Work-Stealing
Optimizing Task Parallelism with Library-Semantics-Aware Compilation
Data Layout Optimization for Portable Performance
Automatic Data Layout Optimizations for GPUs
Performance Impacts with Reliable Parallel File Systems at Exascale Level
Rapid Tomographic Image Reconstruction via Large-Scale Parallelization
Software consolidation as an efficient energy and cost Saving Solution for a SaaS/PaaS Cloud Model
VMPlaceS A Generic Tool to Investigate and Compare VM Placement Algorithms
A Connectivity Model for Agreement in Dynamic Systems
DFEP: Distributed Funding-based Edge Partitioning
PR-STM: Priority Rule Based Software Transactions on the GPU
Leveraging MPI-3 Shared-Memory Extensions for Efficient PGAS Runtime Systems
A Practical Transactional Memory Interface
A Multicore Parallelization of Continuous Skyline Queries on Data Streams
A Fast and Scalable Graph Coloring Algorithm for Multi-core and Many-core Architectures
A Composable Deadlock-Free Approach to Object-Based Isolation
Scalable Data-Driven PageRank: Algorithms, System Issues & Lessons Learned
How Many Threads Will Be Too Many? On the Scalability of OpenMP Implementations
Efficient Nested Dissection for Multicore Architectures
Scheduling Trees of Malleable Tasks for Sparse Linear Algebra
Elastic Tasks: Unifying Task Parallelism and SPMD Parallelism with an Adaptive Runtime
Semi-discrete Matrix-Free Formulation of 3D Elastic Full Waveform Inversion Modeling
10,000 Performance Models per Minute - Scalability of the UG4 Simulation Framework
Exploiting Task-Based Parallelism in Bayesian Uncertainty Quantification
Parallelization of an Advection-Diffusion Problem Arising in Edge Plasma Physics Using Hybrid MPI/OpenMP Programming
Behavioral Non-Portability in Scientific Numeric Computing
Fast Parallel Suffix Array on the GPU
Effective Barrier Synchronization on Intel Xeon Phi Coprocessor
High Performance Multi-GPU SpMV for Multi-component PDE-based Applications
Accelerating Lattice Boltzmann Applications with OpenACC
High-Performance and Scalable Design of MPI-3 RMA on Xeon Phi Clusters
Improving Performance of Convolutional Neural Networks by Separable Filters on GPU
Iterative Sparse Triangular Solves for Preconditioning
Targeting the Parallella
Systematic Fusion of CUDA Kernels for Iterative Sparse Linear System Solvers
Efficient Execution of Multiple CUDA Applications using Transparent Suspend, Resume and Migration
Concurrent Systems: Hybrid Object Implementations and Abortable Objects
Runtime-Aware Architectures
MPI Thread-Level Checking for MPI+OpenMP Applications
2.

電子ブック

EB
edited by Victor Malyshkin
出版情報: Cham : Springer International Publishing : Imprint: Springer, 2015
シリーズ名: Lecture Notes in Computer Science ; 9251
オンライン: http://dx.doi.org/10.1007/978-3-319-21909-7
目次情報: 続きを見る
Parallel models, algorithms and programming methods
Unconventional computing
Cellular automata
Distributed computing
Special processors programming techniques
Applications
Parallel models, algorithms and programming methods
Unconventional computing
Cellular automata
3.

電子ブック

EB
edited by Kentaro Sano, Dimitrios Soudris, Michael Hubner, Pedro C. Diniz
出版情報: Cham : Springer International Publishing : Imprint: Springer, 2015
シリーズ名: Lecture Notes in Computer Science ; 9040
オンライン: http://dx.doi.org/10.1007/978-3-319-16214-0
目次情報: 続きを見る
Architecture and Modeling
Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks
A Vector Caching Scheme for Streaming FPGA SpMV Accelerators
Hierarchical Dynamic Power-Gating in FPGAs
Tools and Compilers
Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation
ArchHDL: A Novel Hardware RTL Design Environment in C++
Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA
Systems and Applications
Preemptive Hardware Multitasking in ReconOS
A Fully Parallel Particle Filter Architecture for FPGAs
TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools
Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures
SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs
Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties
Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components
Network-on-a-Chip Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays
Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip
Survey on Real-Time Network-on-Chip Architectures
Cryptography Applications Efficient SR-Latch PUF
Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study
Dual CLEFIA/AES Cipher Core on FPGA
An Efficient and Flexible FPGA Implementation of a Face Detection System
A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context
A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank
The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs
Extended Abstracts (Posters)
A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures
Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA
A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware
Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures
Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects
Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments
DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems
Acceleration of Data Streaming Classification Using Reconfigurable Technology
On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach
Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform
A Challenge of Portable and High-Speed FPGA Accelerator
Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array
Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture
Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization
DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost
A Flexible Multilayer Perceptron Co-processor for FPGAs
Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs
Towards Performance Modeling of 3D Memory Integrated FPGA Architectures
Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL
Special Session 1: Funded R&D Running and Completed Projects (Invited Papers)
Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing
SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms
Hardware Task Scheduling for Partially Reconfigurable FPGAs
SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring
Special Session 2: Horizon 2020 Funded Projects (Invited Papers)
DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications
Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective
Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach
COSSIM : A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator
Architecture and Modeling
Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks
A Vector Caching Scheme for Streaming FPGA SpMV Accelerators